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Promote armv7a-none-eabihf to Tier 2 #146522
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These commits modify compiler targets. Some changes occurred in src/doc/rustc/src/platform-support cc @Noratrieb |
rustbot has assigned @petrochenkov. Use |
This is the target for 32-bit Cortex-A bare-metal, when using the FPU. The target is well tested by the Embedded Devices Working Group, and the soft-float target (armv7a-none-eabi) is already Tier 2.
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This PR was rebased onto a different master commit. Here's a range-diff highlighting what actually changed. Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers. |
Rebased now #146419 is in. |
Blocked on rust-lang/compiler-team#913. |
… r=jackh726 Demote both armebv7r-none-* targets. OK, slightly more controversial than rust-lang#146520 and rust-lang#146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if `@chrisnc` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once rust-lang#146419 completes the queue.
… r=jackh726 Demote both armebv7r-none-* targets. OK, slightly more controversial than rust-lang#146520 and rust-lang#146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if ``@chrisnc`` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once rust-lang#146419 completes the queue.
… r=jackh726 Demote both armebv7r-none-* targets. OK, slightly more controversial than rust-lang#146520 and rust-lang#146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if ```@chrisnc``` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once rust-lang#146419 completes the queue.
… r=jackh726 Demote both armebv7r-none-* targets. OK, slightly more controversial than rust-lang#146520 and rust-lang#146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if ````@chrisnc```` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once rust-lang#146419 completes the queue.
Rollup merge of #146523 - thejpster:demote-armebv7r-targets, r=jackh726 Demote both armebv7r-none-* targets. OK, slightly more controversial than #146520 and #146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if ````@chrisnc```` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once #146419 completes the queue.
Demote both armebv7r-none-* targets. OK, slightly more controversial than rust-lang/rust#146520 and rust-lang/rust#146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if ````@chrisnc```` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once rust-lang/rust#146419 completes the queue.
The FCP is complete |
@bors r+ |
This PR promotes armv7a-none-eabihf to Tier 2, to join armv7r-none-eabihf and armv7a-none-eabi. I believe it was simply an oversight that it wasn't made Tier 2 before, as most Armv7-A targets have an FPU and it often makes sense to use it.
This PR wil be rebased once #146419 completes the queue.
The
armv7a-none-eabihf
target is for all Arm Cortex-A processors (either 32-bit only, or in 32-bit mode) where the user wants to use the FPU.The Embedded Devices Working Group's Arm Team have just started maintaining this target.
This target is highly similar to a number of existing Tier 2 targets, including
armv7r-none-eabihf
andarmv7a-none-eabi
and so it should not add undue burden.https://doc.rust-lang.org/nightly/rustc/platform-support/armv7a-none-eabi.html was added in #146419. It covers the
-eabi
and the-eabihf
targets.I believe it does.
It uses very similar FPUs to
armv7r-none-eabihf
but is otherwise the same asarmv7a-none-eabi
.It has a full libcore, as per the other arm*-none-* targets.
It should be the same backend as
armv7r-none-eabihf
and friends, except for FPU support, which is already covered inthumbv8m.main-none-eabihf
. There are no issues that I know of.The ABI is EABI, the same as many other Arm targets.
The https://github.com/rust-embedded/cortex-ar repository has been changed in rust-embedded/cortex-ar#57 to build this target with
-Zbuild-std=core
. Locally it seems fine.There are no no-std tests in the tree that I'm aware of.
Building libcore is quite fast.
It does.
Just libcore required (and liballoc). No known issues here.
Noted
The https://github.com/rust-embedded/cortex-ar repository will be changed to use the rustup component when available.
Noted