Fix generated code for MSP430 atomics

.github/workflows/ci.yml

@@ -74,7 +74,8 @@ jobs:
           # Test MSRV
           - { rust: 1.60.0, vendor: Nordic, options: "" }
           # Use nightly for architectures which don't support stable
-          - { rust: nightly, vendor: OTHER, options: "" }
+          - { rust: nightly, vendor: MSP430, options: "--nightly --strict --const_generic --derive_more" }
+          - { rust: nightly, vendor: MSP430, options: "" }
           - { rust: nightly, vendor: Espressif, options: "" }
 
     steps:

CHANGELOG.md

@@ -12,8 +12,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [v0.27.1] - 2022-10-25
 
-- fix cli error with --help/version
+- Fix cli error with --help/version
 - Don't cast fields with width 17-31 and non-zero offset.
+- Fix generated code for MSP430 atomics
 
 ## [v0.27.0] - 2022-10-24
 

ci/script.sh

@@ -460,13 +460,17 @@ main() {
             # test_svd LPC5410x_v0.4
         ;;
 
-        # test other targets (architectures)
-        OTHER)
+        # MSP430
+        MSP430)
             echo '[dependencies.msp430]' >> $td/Cargo.toml
-            echo 'version = "0.3.0"' >> $td/Cargo.toml
+            echo 'version = "0.4.0"' >> $td/Cargo.toml
+
+            echo '[dependencies.msp430-atomic]' >> $td/Cargo.toml
+            echo 'version = "0.1.4"' >> $td/Cargo.toml
 
             # Test MSP430
             test_svd_for_target msp430 https://raw.githubusercontent.com/pftbest/msp430g2553/v0.3.0-svd/msp430g2553.svd
+            test_svd_for_target msp430 https://raw.githubusercontent.com/YuhanLiin/msp430fr2355/rt-up/msp430fr2355.svd
         ;;
 
         # Community-provided RISC-V SVDs

src/generate/generic_msp430_atomic.rs

@@ -1,21 +1,20 @@
 use msp430_atomic::AtomicOperations;
 
-impl<REG: Writable> Reg<REG>
+impl<REG: Readable + Writable> Reg<REG>
 where
-    Self: Readable + Writable,
     REG::Ux: AtomicOperations + Default + core::ops::Not<Output = REG::Ux>,
 {
     /// Set high every bit in the register that was set in the write proxy. Leave other bits
     /// untouched. The write is done in a single atomic instruction.
     #[inline(always)]
     pub unsafe fn set_bits<F>(&self, f: F)
     where
-        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+        F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
     {
-        let bits = f(&mut W {
+        let bits = f(&mut REG::Writer::from(W {
             bits: Default::default(),
             _reg: marker::PhantomData,
-        })
+        }))
         .bits;
         REG::Ux::atomic_or(self.register.as_ptr(), bits);
     }
@@ -25,12 +24,12 @@ where
     #[inline(always)]
     pub unsafe fn clear_bits<F>(&self, f: F)
     where
-        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+        F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
     {
-        let bits = f(&mut W {
+        let bits = f(&mut REG::Writer::from(W {
             bits: !REG::Ux::default(),
             _reg: marker::PhantomData,
-        })
+        }))
         .bits;
         REG::Ux::atomic_and(self.register.as_ptr(), bits);
     }
@@ -40,12 +39,12 @@ where
     #[inline(always)]
     pub unsafe fn toggle_bits<F>(&self, f: F)
     where
-        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+        F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
     {
-        let bits = f(&mut W {
+        let bits = f(&mut REG::Writer::from(W {
             bits: Default::default(),
             _reg: marker::PhantomData,
-        })
+        }))
         .bits;
         REG::Ux::atomic_xor(self.register.as_ptr(), bits);
     }

src/lib.rs

@@ -504,8 +504,8 @@
 //! ```ignore
 //! // These can be called from different contexts even though they are modifying the same register
 //! P1.p1out.set_bits(|w| unsafe { w.bits(1 << 1) });
-//! P1.p1out.clear(|w| unsafe { w.bits(!(1 << 2)) });
-//! P1.p1out.toggle(|w| unsafe { w.bits(1 << 4) });
+//! P1.p1out.clear_bits(|w| unsafe { w.bits(!(1 << 2)) });
+//! P1.p1out.toggle_bits(|w| unsafe { w.bits(1 << 4) });
 //! ```
 #![recursion_limit = "128"]