Updating the managed baselines to x86-64-v2 and armv8-a + lse

docs/design/coreclr/botr/vectors-and-intrinsics.md

@@ -40,8 +40,8 @@ For AOT compilation, the situation is far more complex. This is due to the follo
 
 ## Crossgen2 model of hardware intrinsic usage
 There are 2 sets of instruction sets known to the compiler.
-- The baseline instruction set which defaults to (Sse, Sse2), but may be adjusted via compiler option.
-- The optimistic instruction set which defaults to (Sse3, Ssse3, Sse41, Sse42, Popcnt, Pclmulqdq, and Lzcnt).
+- The baseline instruction set which defaults to x86-64-v2 (SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, and POPCNT), but may be adjusted via compiler option.
+- The optimistic instruction set which defaults to (AES, GFNI, SHA, WAITPKG, and X86SERIALIZE).
 
 Code will be compiled using the optimistic instruction set to drive compilation, but any use of an instruction set beyond the baseline instruction set will be recorded, as will any attempt to use an instruction set beyond the optimistic set if that attempted use has a semantic effect. If the baseline instruction set includes `Avx2` then the size and characteristics of of `Vector<T>` is known. Any other decisions about ABI may also be encoded. For instance, it is likely that the ABI of `Vector256<T>` and `Vector512<T>` will vary based on the presence/absence of `Avx` support.
 

eng/pipelines/common/templates/runtimes/run-test-job.yml

@@ -359,74 +359,31 @@ jobs:
           - jitstress_random_2
         ${{ if in(parameters.testGroup, 'jitstress-isas-arm') }}:
           scenarios:
-          - jitstress_isas_incompletehwintrinsic
           - jitstress_isas_nohwintrinsic
-          - jitstress_isas_nohwintrinsic_nosimd
-          - jitstress_isas_nosimd
         ${{ if in(parameters.testGroup, 'jitstress-isas-x86') }}:
           scenarios:
-          - jitstress_isas_incompletehwintrinsic
           - jitstress_isas_nohwintrinsic
-          - jitstress_isas_nohwintrinsic_nosimd
-          - jitstress_isas_nosimd
           - jitstress_isas_x86_evex
-          - jitstress_isas_x86_noaes
           - jitstress_isas_x86_noavx
           - jitstress_isas_x86_noavx2
           - jitstress_isas_x86_noavx512
-          - jitstress_isas_x86_nobmi1
-          - jitstress_isas_x86_nobmi2
-          - jitstress_isas_x86_nofma
-          - jitstress_isas_x86_nohwintrinsic
-          - jitstress_isas_x86_nolzcnt
-          - jitstress_isas_x86_nopclmulqdq
-          - jitstress_isas_x86_nopopcnt
-          - jitstress_isas_x86_nosse
-          - jitstress_isas_x86_nosse2
-          - jitstress_isas_x86_nosse3
-          - jitstress_isas_x86_nosse3_4
-          - jitstress_isas_x86_nosse41
-          - jitstress_isas_x86_nosse42
-          - jitstress_isas_x86_nossse3
           - jitstress_isas_x86_vectort128
           - jitstress_isas_x86_vectort512
           - jitstress_isas_x86_noavx512_vectort128
-          - jitstress_isas_1_x86_noaes
+          - jitstress_isas_1_x86_evex
           - jitstress_isas_1_x86_noavx
           - jitstress_isas_1_x86_noavx2
           - jitstress_isas_1_x86_noavx512
-          - jitstress_isas_1_x86_nobmi1
-          - jitstress_isas_1_x86_nobmi2
-          - jitstress_isas_1_x86_nofma
-          - jitstress_isas_1_x86_nohwintrinsic
-          - jitstress_isas_1_x86_nolzcnt
-          - jitstress_isas_1_x86_nopclmulqdq
-          - jitstress_isas_1_x86_nopopcnt
-          - jitstress_isas_1_x86_nosse
-          - jitstress_isas_1_x86_nosse2
-          - jitstress_isas_1_x86_nosse3
-          - jitstress_isas_1_x86_nosse3_4
-          - jitstress_isas_1_x86_nosse41
-          - jitstress_isas_1_x86_nosse42
-          - jitstress_isas_1_x86_nossse3
-          - jitstress_isas_2_x86_noaes
+          - jitstress_isas_1_x86_vectort128
+          - jitstress_isas_1_x86_vectort512
+          - jitstress_isas_1_x86_noavx512_vectort128
+          - jitstress_isas_2_x86_evex
           - jitstress_isas_2_x86_noavx
           - jitstress_isas_2_x86_noavx2
           - jitstress_isas_2_x86_noavx512
-          - jitstress_isas_2_x86_nobmi1
-          - jitstress_isas_2_x86_nobmi2
-          - jitstress_isas_2_x86_nofma
-          - jitstress_isas_2_x86_nohwintrinsic
-          - jitstress_isas_2_x86_nolzcnt
-          - jitstress_isas_2_x86_nopclmulqdq
-          - jitstress_isas_2_x86_nopopcnt
-          - jitstress_isas_2_x86_nosse
-          - jitstress_isas_2_x86_nosse2
-          - jitstress_isas_2_x86_nosse3
-          - jitstress_isas_2_x86_nosse3_4
-          - jitstress_isas_2_x86_nosse41
-          - jitstress_isas_2_x86_nosse42
-          - jitstress_isas_2_x86_nossse3
+          - jitstress_isas_2_x86_vectort128
+          - jitstress_isas_2_x86_vectort512
+          - jitstress_isas_2_x86_noavx512_vectort128
         ${{ if in(parameters.testGroup, 'jitstress-isas-avx512') }}:
           scenarios:
           - jitstress_isas_x86_evex

src/coreclr/inc/clrconfigvalues.h

@@ -669,7 +669,6 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableHWIntrinsic,            W("EnableHWIntri
 #endif // defined(TARGET_LOONGARCH64)
 
 #if defined(TARGET_AMD64) || defined(TARGET_X86)
-RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableSSE42,                  W("EnableSSE42"),               1, "Allows SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, and dependent hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX,                    W("EnableAVX"),                 1, "Allows AVX and dependent hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX2,                   W("EnableAVX2"),                1, "Allows AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE and dependent hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512,                 W("EnableAVX512"),              1, "Allows AVX512 F+BW+CD+DQ+VL and depdendent hardware intrinsics to be disabled")