@@ -1149,7 +1149,6 @@ def SYCLDevice : InheritableAttr {
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let Subjects = SubjectList<[Function]>;
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let LangOpts = [SYCLIsDevice];
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let Documentation = [SYCLDeviceDocs];
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- let PragmaAttributeSupport = 0;
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}
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def SYCLKernel : InheritableAttr {
@@ -1167,7 +1166,6 @@ def SYCLSimd : InheritableAttr {
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let Subjects = SubjectList<[Function]>;
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let LangOpts = [SYCLExplicitSIMD];
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let Documentation = [SYCLSimdDocs];
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- let PragmaAttributeSupport = 0;
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}
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// Available in SYCL explicit SIMD extension. Binds a file scope private
@@ -1180,7 +1178,6 @@ def SYCLRegisterNum : InheritableAttr {
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// for the host device as well
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let LangOpts = [SYCLExplicitSIMD];
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let Documentation = [SYCLRegisterNumDocs];
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- let PragmaAttributeSupport = 0;
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}
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// Used to mark ESIMD kernel pointer parameters originating from accessors.
@@ -1190,7 +1187,6 @@ def SYCLSimdAccessorPtr : InheritableAttr {
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let Subjects = SubjectList<[ParmVar]>;
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let LangOpts = [SYCLExplicitSIMD];
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let Documentation = [SYCLSimdAccessorPtrDocs];
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- let PragmaAttributeSupport = 0;
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}
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def SYCLScope : Attr {
@@ -1219,7 +1215,6 @@ def SYCLDeviceIndirectlyCallable : InheritableAttr {
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let Subjects = SubjectList<[Function]>;
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let LangOpts = [SYCLIsDevice];
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let Documentation = [SYCLDeviceIndirectlyCallableDocs];
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- let PragmaAttributeSupport = 0;
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}
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def SYCLIntelBufferLocation : InheritableAttr {
@@ -1244,7 +1239,6 @@ def SYCLIntelKernelArgsRestrict : InheritableAttr {
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let LangOpts = [ SYCLIsDevice, SYCLIsHost ];
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let Documentation = [ SYCLIntelKernelArgsRestrictDocs ];
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let SimpleHandler = 1;
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- let PragmaAttributeSupport = 0;
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}
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def SYCLIntelNumSimdWorkItems : InheritableAttr {
@@ -1254,7 +1248,6 @@ def SYCLIntelNumSimdWorkItems : InheritableAttr {
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let LangOpts = [SYCLIsDevice, SYCLIsHost];
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let Subjects = SubjectList<[Function], ErrorDiag>;
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let Documentation = [SYCLIntelNumSimdWorkItemsAttrDocs];
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- let PragmaAttributeSupport = 0;
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}
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def SYCLIntelUseStallEnableClusters : InheritableAttr {
@@ -1267,7 +1260,6 @@ def SYCLIntelUseStallEnableClusters : InheritableAttr {
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}
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}];
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let Documentation = [SYCLIntelUseStallEnableClustersAttrDocs];
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- let PragmaAttributeSupport = 0;
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}
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def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
@@ -1277,7 +1269,6 @@ def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
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let LangOpts = [SYCLIsDevice, SYCLIsHost];
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let Subjects = SubjectList<[Function], ErrorDiag>;
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let Documentation = [SYCLIntelSchedulerTargetFmaxMhzAttrDocs];
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- let PragmaAttributeSupport = 0;
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let AdditionalMembers = [{
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static unsigned getMinValue() {
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return 0;
@@ -1286,7 +1277,6 @@ def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
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return 1024*1024;
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}
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}];
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-
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}
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def SYCLIntelMaxWorkGroupSize : InheritableAttr {
@@ -1297,11 +1287,19 @@ def SYCLIntelMaxWorkGroupSize : InheritableAttr {
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ExprArgument<"ZDim">];
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let LangOpts = [SYCLIsDevice, SYCLIsHost];
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let Subjects = SubjectList<[Function], ErrorDiag>;
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- let PragmaAttributeSupport = 0;
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let AdditionalMembers = [{
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ArrayRef<const Expr *> dimensions() const {
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return {getXDim(), getYDim(), getZDim()};
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}
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+ Optional<llvm::APSInt> getXDimVal(ASTContext &Ctx) const {
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+ return getXDim()->getIntegerConstantExpr(Ctx);
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+ }
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+ Optional<llvm::APSInt> getYDimVal(ASTContext &Ctx) const {
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+ return getYDim()->getIntegerConstantExpr(Ctx);
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+ }
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+ Optional<llvm::APSInt> getZDimVal(ASTContext &Ctx) const {
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+ return getZDim()->getIntegerConstantExpr(Ctx);
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+ }
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}];
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let Documentation = [SYCLIntelMaxWorkGroupSizeAttrDocs];
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}
@@ -1313,7 +1311,6 @@ def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
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let LangOpts = [SYCLIsDevice, SYCLIsHost];
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let Subjects = SubjectList<[Function], ErrorDiag>;
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let Documentation = [SYCLIntelMaxGlobalWorkDimAttrDocs];
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- let PragmaAttributeSupport = 0;
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}
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def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
@@ -1323,7 +1320,6 @@ def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
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let LangOpts = [SYCLIsDevice, SYCLIsHost];
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let Subjects = SubjectList<[Function], ErrorDiag>;
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let Documentation = [SYCLIntelNoGlobalWorkOffsetAttrDocs];
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- let PragmaAttributeSupport = 0;
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}
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def SYCLIntelLoopFuse : InheritableAttr {
@@ -1404,7 +1400,6 @@ def IntelReqdSubGroupSize: InheritableAttr {
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let Subjects = SubjectList<[Function, CXXMethod], ErrorDiag>;
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let Documentation = [IntelReqdSubGroupSizeDocs];
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let LangOpts = [OpenCL, SYCLIsDevice, SYCLIsHost];
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- let PragmaAttributeSupport = 0;
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}
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// This attribute is both a type attribute, and a declaration attribute (for
@@ -2124,7 +2119,6 @@ def SYCLIntelPipeIO : Attr {
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let LangOpts = [SYCLIsDevice, SYCLIsHost];
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let Subjects = SubjectList<[Var]>;
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let Documentation = [SYCLIntelPipeIOAttrDocs];
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- let PragmaAttributeSupport = 0;
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}
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// Variadic integral arguments.
@@ -2853,6 +2847,15 @@ def ReqdWorkGroupSize : InheritableAttr {
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ArrayRef<const Expr *> dimensions() const {
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return {getXDim(), getYDim(), getZDim()};
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}
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+ Optional<llvm::APSInt> getXDimVal(ASTContext &Ctx) const {
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+ return getXDim()->getIntegerConstantExpr(Ctx);
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+ }
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+ Optional<llvm::APSInt> getYDimVal(ASTContext &Ctx) const {
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+ return getYDim()->getIntegerConstantExpr(Ctx);
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+ }
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+ Optional<llvm::APSInt> getZDimVal(ASTContext &Ctx) const {
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+ return getZDim()->getIntegerConstantExpr(Ctx);
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+ }
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}];
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let Documentation = [ReqdWorkGroupSizeAttrDocs];
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}
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