Support SPARC and SPARC64 (experimental)

Author: taiki-e

.github/.cspell/project-dictionary.txt

@@ -39,6 +39,7 @@ ldrex
 ldrexd
 ldsetp
 ldxp
+leoncasa
 lgcc
 libunwind
 linkall
@@ -49,6 +50,7 @@ lwarx
 lwsync
 machdep
 mcpu
+membar
 memd
 memw
 mfcr
@@ -97,6 +99,7 @@ stxp
 subarch
 swpp
 uart
+ultrasparc
 usart
 uwrite
 uwriteln

.github/workflows/ci.yml

@@ -234,6 +234,13 @@ jobs:
             target: s390x-unknown-linux-gnu
           - rust: nightly
             target: s390x-unknown-linux-gnu
+          - rust: nightly
+            target: sparc-unknown-linux-gnu
+            flags: -C target-cpu=leon4
+          - rust: nightly-2024-11-08 # Rust 1.84, LLVM 19 (oldest version we can use asm_experimental_arch on this target)
+            target: sparc64-unknown-linux-gnu
+          - rust: nightly
+            target: sparc64-unknown-linux-gnu
           - rust: '1.59' # LLVM 13
             target: thumbv7neon-unknown-linux-gnueabihf
           - rust: '1.74' # LLVM 17 (oldest version that MaybeUninit register is supported)

README.md

@@ -18,7 +18,7 @@ This crate provides a way to soundly perform such operations.
 
 ## Platform Support
 
-Currently, x86, x86_64, Arm, AArch64, RISC-V, LoongArch64, MIPS32, MIPS64, PowerPC, s390x, MSP430, Arm64EC, AVR, Hexagon, M68k, and Xtensa are supported.
+Currently, x86, x86_64, Arm, AArch64, RISC-V, LoongArch64, MIPS32, MIPS64, PowerPC, s390x, MSP430, Arm64EC, AVR, SPARC, Hexagon, M68k, and Xtensa are supported.
 
 | target_arch                      | primitives                                          | load/store | swap/CAS |
 | -------------------------------- | --------------------------------------------------- |:----------:|:--------:|
@@ -40,6 +40,8 @@ Currently, x86, x86_64, Arm, AArch64, RISC-V, LoongArch64, MIPS32, MIPS64, Power
 | arm64ec \[4]                     | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128 | ✓          | ✓        |
 | msp430 \[4] (experimental)       | isize,usize,i8,u8,i16,u16                           | ✓          | ✓        |
 | avr \[4] (experimental)          | isize,usize,i8,u8,i16,u16                           | ✓          | ✓        |
+| sparc \[4] \[7] (experimental)   | isize,usize,i8,u8,i16,u16,i32,u32                   | ✓          | ✓        |
+| sparc64 \[4] (experimental)      | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64           | ✓          | ✓        |
 | hexagon \[4] (experimental)      | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64           | ✓          | ✓        |
 | m68k \[4] (experimental)         | isize,usize,i8,u8,i16,u16,i32,u32                   | ✓          | ✓\[1]    |
 | xtensa \[4] (experimental)       | isize,usize,i8,u8,i16,u16,i32,u32                   | ✓          | ✓\[1]    |
@@ -50,6 +52,7 @@ Currently, x86, x86_64, Arm, AArch64, RISC-V, LoongArch64, MIPS32, MIPS64, Power
 \[4] Requires nightly due to `#![feature(asm_experimental_arch)]`.<br>
 \[5] Requires cmpxchg16b target feature (enabled by default on Apple and Windows (except Windows 7) targets).<br>
 \[6] Requires target-cpu pwr8+ (powerpc64le is pwr8 by default).<br>
+\[7] Requires CAS instruction support.<br>
 
 Feel free to submit an issue if your target is not supported yet.
 

build.rs

@@ -30,7 +30,7 @@ fn main() {
 
     if version.minor >= 80 {
         println!(
-            r#"cargo:rustc-check-cfg=cfg(target_feature,values("x87","v8m","fast-serialization","isa-68020"))"#
+            r#"cargo:rustc-check-cfg=cfg(target_feature,values("x87","v8m","fast-serialization","leoncasa","v9","isa-68020"))"#
         );
 
         // Custom cfgs set by build script. Not public API.
@@ -41,7 +41,7 @@ fn main() {
         // TODO: handle multi-line target_feature_fallback
         // grep -F 'target_feature_fallback("' build.rs | grep -Ev '^ *//' | sed -E 's/^.*target_feature_fallback\(//; s/",.*$/"/' | LC_ALL=C sort -u | tr '\n' ',' | sed -E 's/,$/\n/'
         println!(
-            r#"cargo:rustc-check-cfg=cfg(atomic_maybe_uninit_target_feature,values("a","cmpxchg16b","fast-serialization","isa-68020","lse","lse128","lse2","mclass","partword-atomics","quadword-atomics","rcpc","rcpc3","v5te","v6","v7","v8","v8m","x87","zaamo","zabha"))"#
+            r#"cargo:rustc-check-cfg=cfg(atomic_maybe_uninit_target_feature,values("a","cmpxchg16b","fast-serialization","isa-68020","leoncasa","lse","lse128","lse2","mclass","partword-atomics","quadword-atomics","rcpc","rcpc3","v5te","v6","v7","v8","v8m","v9","x87","zaamo","zabha"))"#
         );
     }
 
@@ -107,6 +107,15 @@ fn main() {
                 println!("cargo:rustc-cfg=atomic_maybe_uninit_unstable_asm_experimental_arch");
             }
         }
+        // https://github.com/rust-lang/rust/pull/132472 merged in Rust 1.84 (nightly-2024-11-08).
+        "sparc" | "sparc64" => {
+            if version.nightly
+                && version.probe(84, 2024, 11, 7)
+                && is_allowed_feature("asm_experimental_arch")
+            {
+                println!("cargo:rustc-cfg=atomic_maybe_uninit_unstable_asm_experimental_arch");
+            }
+        }
         _ => {}
     }
 
@@ -351,6 +360,32 @@ fn main() {
             // bcr 14,0
             target_feature_fallback("fast-serialization", arch9_features);
         }
+        "sparc" => {
+            let mut leoncasa = false;
+            let mut v9 = false;
+            if let Some(cpu) = target_cpu() {
+                // https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Sparc/Sparc.td
+                match &*cpu {
+                    "myriad2" | "myriad2.1" | "myriad2.2" | "myriad2.3" | "ma2100" | "ma2150"
+                    | "ma2155" | "ma2450" | "ma2455" | "ma2x5x" | "ma2080" | "ma2085"
+                    | "ma2480" | "ma2485" | "ma2x8x" | "gr712rc" | "leon4" | "gr740" => {
+                        leoncasa = true;
+                    }
+                    "v9" | "ultrasparc" | "ultrasparc3" | "niagara" | "niagara2" | "niagara3"
+                    | "niagara4" => v9 = true,
+                    _ => {}
+                }
+            } else {
+                // https://github.com/llvm/llvm-project/pull/109278
+                // https://github.com/rust-lang/rust/blob/1.82.0/compiler/rustc_target/src/spec/targets/sparc_unknown_linux_gnu.rs#L17
+                v9 = target_os == "linux" || target_os == "solaris";
+            }
+            // As of rustc 1.82, target_feature "leoncasa"/"v9" is not available on rustc side:
+            // https://github.com/rust-lang/rust/blob/1.82.0/compiler/rustc_target/src/target_features.rs
+            // (will be added in https://github.com/rust-lang/rust/pull/132552)
+            target_feature_fallback("leoncasa", leoncasa);
+            target_feature_fallback("v9", v9);
+        }
         "m68k" => {
             // https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/M68k/M68k.td
             // Linux requires M68020+.

src/arch/cfgs/sparc.rs

@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+
+#![allow(missing_docs)]
+
+#[macro_export]
+macro_rules! cfg_has_atomic_8 {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[macro_export]
+macro_rules! cfg_no_atomic_8 {
+    ($($tt:tt)*) => {};
+}
+#[macro_export]
+macro_rules! cfg_has_atomic_16 {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[macro_export]
+macro_rules! cfg_no_atomic_16 {
+    ($($tt:tt)*) => {};
+}
+#[macro_export]
+macro_rules! cfg_has_atomic_32 {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[macro_export]
+macro_rules! cfg_no_atomic_32 {
+    ($($tt:tt)*) => {};
+}
+// TODO: V8+ with 64-bit g/o reg
+#[cfg(target_arch = "sparc")]
+#[macro_export]
+macro_rules! cfg_has_atomic_64 {
+    ($($tt:tt)*) => {};
+}
+// TODO: V8+ with 64-bit g/o reg
+#[cfg(target_arch = "sparc")]
+#[macro_export]
+macro_rules! cfg_no_atomic_64 {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[cfg(target_arch = "sparc64")]
+#[macro_export]
+macro_rules! cfg_has_atomic_64 {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[cfg(target_arch = "sparc64")]
+#[macro_export]
+macro_rules! cfg_no_atomic_64 {
+    ($($tt:tt)*) => {};
+}
+#[macro_export]
+macro_rules! cfg_has_atomic_128 {
+    ($($tt:tt)*) => {};
+}
+#[macro_export]
+macro_rules! cfg_no_atomic_128 {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[macro_export]
+macro_rules! cfg_has_atomic_cas {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[macro_export]
+macro_rules! cfg_no_atomic_cas {
+    ($($tt:tt)*) => {};
+}

src/arch/mod.rs

@@ -39,6 +39,16 @@
             target_arch = "powerpc",
             target_arch = "powerpc64",
             target_arch = "s390x",
+            all(
+                target_arch = "sparc",
+                any(
+                    target_feature = "leoncasa",
+                    atomic_maybe_uninit_target_feature = "leoncasa",
+                    target_feature = "v9",
+                    atomic_maybe_uninit_target_feature = "v9",
+                ),
+            ),
+            target_arch = "sparc64",
             target_arch = "xtensa",
         ),
         atomic_maybe_uninit_unstable_asm_experimental_arch,
@@ -108,6 +118,20 @@ mod riscv;
 #[cfg(atomic_maybe_uninit_unstable_asm_experimental_arch)]
 #[cfg_attr(atomic_maybe_uninit_s390x_no_reg_addr, path = "s390x_no_reg_addr.rs")]
 mod s390x;
+#[cfg(any(
+    all(
+        target_arch = "sparc",
+        any(
+            target_feature = "leoncasa",
+            atomic_maybe_uninit_target_feature = "leoncasa",
+            target_feature = "v9",
+            atomic_maybe_uninit_target_feature = "v9",
+        ),
+    ),
+    target_arch = "sparc64",
+))]
+#[cfg(atomic_maybe_uninit_unstable_asm_experimental_arch)]
+mod sparc;
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 mod x86;
 #[cfg(target_arch = "xtensa")]