From 9cc6a7cb3ec511e8424034094cfb1aeed050b6a2 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 13 Aug 2024 12:25:48 -0700 Subject: [PATCH] [Mips] Fix fast isel for i16 bswap. We need to mask the SRL result to 8 bits before ORing in the SLL. This is needed in case bits 23:16 of the input aren't zero. They will have been shifted into bits 15:8. We don't need to AND the result with 0xffff. It's ok if the upper 16 bits of the register is garbage. Fixes #103035. --- llvm/lib/Target/Mips/MipsFastISel.cpp | 4 ++-- llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp index 3485825b77627..7d8278c8ca3cf 100644 --- a/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -1608,8 +1608,8 @@ bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { } emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8); emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8); - emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]); - emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF); + emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[1]).addImm(0xFF); + emitInst(Mips::OR, DestReg).addReg(TempReg[0]).addReg(TempReg[2]); updateValueMap(II, DestReg); return true; } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll index bd762a0e1d741..ce664c78e86c2 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll @@ -21,8 +21,8 @@ define void @b16() { ; 32R1: sll $[[TMP1:[0-9]+]], $[[A_VAL]], 8 ; 32R1: srl $[[TMP2:[0-9]+]], $[[A_VAL]], 8 - ; 32R1: or $[[TMP3:[0-9]+]], $[[TMP1]], $[[TMP2]] - ; 32R1: andi $[[TMP4:[0-9]+]], $[[TMP3]], 65535 + ; 32R1: andi $[[TMP3:[0-9]+]], $[[TMP2]], 255 + ; 32R1: or $[[RESULT:[0-9]+]], $[[TMP1]], $[[TMP3]] ; 32R2: wsbh $[[RESULT:[0-9]+]], $[[A_VAL]]