add subreg case

Author: broxigarchen

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -7527,6 +7527,11 @@ void SIInstrInfo::legalizeOperandsVALUt16(MachineInstr &MI, unsigned OpIdx,
     return;
 
   unsigned Opcode = MI.getOpcode();
+  if (Opcode == AMDGPU::REG_SEQUENCE) {
+    legalizeSpecialInst_t16(MI, MRI);
+    return;
+  }
+
   MachineBasicBlock *MBB = MI.getParent();
   // Legalize operands and check for size mismatch
   if (!OpIdx || OpIdx >= MI.getNumExplicitOperands() ||
@@ -7565,50 +7570,63 @@ void SIInstrInfo::legalizeOperandsVALUt16(MachineInstr &MI,
     legalizeOperandsVALUt16(MI, OpIdx, MRI);
 }
 
-// Legalize size mismatches between 16bit and 32bit registers in v2s copy
-// lowering (lower the copy itself). Including cases:
-// 1. sreg32 = copy vgpr16 => vgpr32 = REG_SEQUENCE(vgpr16, lo16)
-// 2. sreg32 = copy .lo16:vgpr32 / sreg32 = copy .hi16:vgpr32
-//    =>  vgpr16 = copy .hi/lo16:vgpr32
-//        vgpr32 = REG_SEQUENCE(vgpr16, lo16)
+// Legalize operands of size-mismatches special inst between 16bit and 32bit
+// in moveToVALU lowering in true16 mode. This caused by 16bit
+// placed in both vgpr16 and sreg32 by isel. Including cases:
+// Copy
+// 1. dst32 = copy vgpr16 => dst32 = REG_SEQUENCE(vgpr16, lo16)
+// 2. dst32 = copy .lo16:vgpr32 / dst32 = copy .hi16:vgpr32
+//    => dst32 = REG_SEQUENCE(.lo16/hi16:vgpr32, lo16)
 // 3. sgpr16 = copy vgpr32/... (skipped, isel do not generate sgpr16)
+//
+// Reg_sequence
+// dst32 = reg_sequence(vgpr32, lo16/hi16)
+//    => dst32 = reg_sequence(.lo16:vgpr32, lo16/hi16)
+//
 // This can be removed after we have sgpr16 in place.
-bool SIInstrInfo::legalizeV2SCopyt16(MachineInstr &Copy,
-                                     MachineRegisterInfo &MRI,
-                                     SIInstrWorklist &Worklist) const {
-  Register DstReg = Copy.getOperand(0).getReg();
-  Register SrcReg = Copy.getOperand(1).getReg();
-  Register SrcSubReg = Copy.getOperand(1).getSubReg();
-  const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(Copy);
-  const TargetRegisterClass *SrcRegRC = getOpRegClass(Copy, 1);
-  bool KeepCopy;
-
-  if (RI.getMatchingSuperRegClass(NewDstRC, SrcRegRC, AMDGPU::lo16)) {
-    KeepCopy = 0;
-  } else if (NewDstRC == &AMDGPU::VGPR_32RegClass &&
-             (SrcSubReg == AMDGPU::hi16 || SrcSubReg == AMDGPU::lo16)) {
-    KeepCopy = 1;
-    Register NewDstReg = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
-    Copy.getOperand(0).setReg(NewDstReg);
-    SrcReg = NewDstReg;
-  } else
-    return false;
+void SIInstrInfo::legalizeSpecialInst_t16(MachineInstr &Inst,
+                                          MachineRegisterInfo &MRI) const {
+  unsigned Opcode = Inst.getOpcode();
+  const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(Inst);
+  switch (Opcode) {
+  case AMDGPU::COPY: {
+    Register SrcReg = Inst.getOperand(1).getReg();
+    if (!SrcReg.isVirtual() || !RI.isVGPR(MRI, SrcReg))
+      return;
 
-  Register NewDstReg = MRI.createVirtualRegister(NewDstRC);
-  Register Undef = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
-  BuildMI(*Copy.getParent(), &Copy, Copy.getDebugLoc(),
-          get(AMDGPU::IMPLICIT_DEF), Undef);
-  BuildMI(*Copy.getParent(), std::next(Copy.getIterator()), Copy.getDebugLoc(),
-          get(AMDGPU::REG_SEQUENCE), NewDstReg)
-      .addReg(SrcReg)
-      .addImm(AMDGPU::lo16)
-      .addReg(Undef)
-      .addImm(AMDGPU::hi16);
-  if (!KeepCopy)
-    Copy.eraseFromParent();
-  MRI.replaceRegWith(DstReg, NewDstReg);
-  addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
-  return true;
+    bool SetSubReg = false;
+    Register SrcSubReg = Inst.getOperand(1).getSubReg();
+    const TargetRegisterClass *SrcRegRC = getOpRegClass(Inst, 1);
+    if (RI.getMatchingSuperRegClass(NewDstRC, SrcRegRC, AMDGPU::lo16)) {
+    } else if (NewDstRC == &AMDGPU::VGPR_32RegClass &&
+               (SrcSubReg == AMDGPU::hi16 || SrcSubReg == AMDGPU::lo16)) {
+      SetSubReg = true;
+    } else
+      return;
+
+    Register Undef = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
+    BuildMI(*Inst.getParent(), &Inst, Inst.getDebugLoc(),
+            get(AMDGPU::IMPLICIT_DEF), Undef);
+    Inst.setDesc(get(AMDGPU::REG_SEQUENCE));
+    if (SetSubReg)
+      Inst.getOperand(1).setSubReg(SrcSubReg);
+
+    Inst.addOperand(MachineOperand::CreateImm(AMDGPU::lo16));
+    Inst.addOperand(MachineOperand::CreateReg(Undef, 0));
+    Inst.addOperand(MachineOperand::CreateImm(AMDGPU::hi16));
+  } break;
+  case AMDGPU::REG_SEQUENCE: {
+    for (unsigned I = 0, E = (Inst.getNumOperands() - 1) / 2; I < E; ++I) {
+      Register SrcReg = Inst.getOperand(1 + 2 * I).getReg();
+      auto SubReg = Inst.getOperand(1 + 2 * I + 1).getImm();
+      if (SrcReg.isVirtual() && RI.isVGPR(MRI, SrcReg) &&
+          MRI.constrainRegClass(SrcReg, &AMDGPU::VGPR_32RegClass) &&
+          (SubReg == AMDGPU::lo16 || SubReg == AMDGPU::hi16)) {
+        Inst.getOperand(1 + 2 * I).setSubReg(AMDGPU::lo16);
+      }
+    }
+  } break;
+  }
 }
 
 void SIInstrInfo::moveToVALU(SIInstrWorklist &Worklist,
@@ -8129,14 +8147,8 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
       return;
     }
 
-    // If this is a v2s copy between 16bit and 32bit reg,
-    // replace vgpr copy to reg_sequence
-    if (ST.useRealTrue16Insts() && Inst.isCopy() &&
-        Inst.getOperand(1).getReg().isVirtual() &&
-        RI.isVGPR(MRI, Inst.getOperand(1).getReg())) {
-      if (legalizeV2SCopyt16(Inst, MRI, Worklist))
-        return;
-    }
+    if (ST.useRealTrue16Insts())
+      legalizeSpecialInst_t16(Inst, MRI);
 
     if (Inst.isCopy() && Inst.getOperand(1).getReg().isVirtual() &&
         NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) {

llvm/lib/Target/AMDGPU/SIInstrInfo.h

@@ -1375,8 +1375,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
                                MachineRegisterInfo &MRI) const;
   void legalizeOperandsVALUt16(MachineInstr &Inst, unsigned OpIdx,
                                MachineRegisterInfo &MRI) const;
-  bool legalizeV2SCopyt16(MachineInstr &Inst, MachineRegisterInfo &MRI,
-                          SIInstrWorklist &Worklist) const;
+  void legalizeSpecialInst_t16(MachineInstr &Inst,
+                               MachineRegisterInfo &MRI) const;
 
   /// Replace the instructions opcode with the equivalent VALU
   /// opcode.  This function will also move the users of MachineInstruntions

llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir

@@ -138,8 +138,7 @@ body:             |
     ; GCN-LABEL: name: copy_vgpr16_sreg32_lo16_usedby_salu16
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
-    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[DEF]].lo16
-    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY]], %subreg.lo16, [[DEF1]], %subreg.hi16
+    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[DEF]].lo16, %subreg.lo16, [[DEF1]], %subreg.hi16
     ; GCN-NEXT: [[V_TRUNC_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_TRUNC_F16_t16_e64 0, [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
     %0:vgpr_32 = IMPLICIT_DEF
     %1:sreg_32 = COPY %0.lo16:vgpr_32
@@ -153,8 +152,7 @@ body:             |
     ; GCN-LABEL: name: copy_vgpr16_sreg32_hi16_usedby_salu16
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
-    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[DEF]].hi16
-    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY]], %subreg.lo16, [[DEF1]], %subreg.hi16
+    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[DEF]].hi16, %subreg.lo16, [[DEF1]], %subreg.hi16
     ; GCN-NEXT: [[V_TRUNC_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_TRUNC_F16_t16_e64 0, [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
     %0:vgpr_32 = IMPLICIT_DEF
     %1:sreg_32 = COPY %0.hi16:vgpr_32
@@ -188,21 +186,17 @@ body:             |
 ...
 
 ---
-name:            S_FMAC_F16
+name:            reg_sequence_vgpr32_sreg32
 body:             |
   bb.0:
-    ; GCN-LABEL: name: S_FMAC_F16
+    ; GCN-LABEL: name: reg_sequence_vgpr32_sreg32
     ; GCN: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
-    ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
-    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[DEF]], %subreg.lo16, [[DEF1]], %subreg.hi16
-    ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
-    ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[DEF]], %subreg.lo16, [[DEF2]], %subreg.hi16
-    ; GCN-NEXT: [[V_FMAC_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_FMAC_F16_t16_e64 0, [[REG_SEQUENCE1]].lo16, 0, [[REG_SEQUENCE1]].lo16, 0, [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+    ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[DEF1]].lo16, %subreg.lo16, [[DEF]], %subreg.hi16
     %0:vgpr_16 = IMPLICIT_DEF
-    %1:sgpr_lo16 = COPY %0:vgpr_16
-    %2:sreg_32 = COPY %0:vgpr_16
-    %3:sreg_32 = COPY %1:sgpr_lo16
-    %4:sreg_32 = S_FMAC_F16 %3:sreg_32, %3:sreg_32, %2:sreg_32, implicit $mode
+    %1:vgpr_32 = IMPLICIT_DEF
+    %2:sreg_32 = COPY %1:vgpr_32
+    %3:vgpr_32 = REG_SEQUENCE %2:sreg_32, %subreg.lo16, %0:vgpr_16, %subreg.hi16
 ...
 
 ---