diff --git a/rust-toolchain.toml b/rust-toolchain.toml
index 6340b70394..1413b634dd 100644
--- a/rust-toolchain.toml
+++ b/rust-toolchain.toml
@@ -1,5 +1,5 @@
 [toolchain]
-channel = "nightly-2024-06-01"
+channel = "nightly-2024-06-18"
 components = [
     "llvm-tools",
     "rust-src",
diff --git a/src/arch/riscv64/kernel/scheduler.rs b/src/arch/riscv64/kernel/scheduler.rs
index 64bd1a5a94..b820f4a031 100644
--- a/src/arch/riscv64/kernel/scheduler.rs
+++ b/src/arch/riscv64/kernel/scheduler.rs
@@ -160,7 +160,8 @@ impl TaskStacks {
 		unsafe {
 			ptr::write_bytes(
 				(virt_addr
-					+ KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE
+					+ KERNEL_STACK_SIZE
+					+ DEFAULT_STACK_SIZE
 					+ 3 * BasePageSize::SIZE as usize)
 					//(virt_addr + KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE)
 					.as_mut_ptr::<u8>(),
@@ -198,7 +199,8 @@ impl TaskStacks {
 			TaskStacks::Boot(_) => VirtAddr::zero(),
 			TaskStacks::Common(stacks) => {
 				stacks.virt_addr
-					+ KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE
+					+ KERNEL_STACK_SIZE
+					+ DEFAULT_STACK_SIZE
 					+ 3 * BasePageSize::SIZE as usize
 				//stacks.virt_addr + KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE
 			}
@@ -280,7 +282,7 @@ impl TaskTLS {
 		// Yes, it does, so we have to allocate TLS memory.
 		// Allocate enough space for the given size and one more variable of type usize, which holds the tls_pointer.
 		let tls_allocation_size = tls_size.align_up(32usize); // + mem::size_of::<usize>();
-													  // We allocate in 128 byte granularity (= cache line size) to avoid false sharing
+														// We allocate in 128 byte granularity (= cache line size) to avoid false sharing
 		let memory_size = tls_allocation_size.align_up(128usize);
 		let layout =
 			Layout::from_size_align(memory_size, 128).expect("TLS has an invalid size / alignment");
diff --git a/src/arch/x86_64/kernel/apic.rs b/src/arch/x86_64/kernel/apic.rs
index 39b54d1ecb..983d55df90 100644
--- a/src/arch/x86_64/kernel/apic.rs
+++ b/src/arch/x86_64/kernel/apic.rs
@@ -825,7 +825,8 @@ pub fn ipi_tlb_flush() {
 					local_apic_write(
 						IA32_X2APIC_ICR,
 						destination
-							| APIC_ICR_LEVEL_ASSERT | APIC_ICR_DELIVERY_MODE_FIXED
+							| APIC_ICR_LEVEL_ASSERT
+							| APIC_ICR_DELIVERY_MODE_FIXED
 							| u64::from(TLB_FLUSH_INTERRUPT_NUMBER),
 					);
 				}
diff --git a/src/drivers/pci.rs b/src/drivers/pci.rs
index 7b27360113..95020e2d51 100644
--- a/src/drivers/pci.rs
+++ b/src/drivers/pci.rs
@@ -283,7 +283,8 @@ impl<T: ConfigRegionAccess> fmt::Display for PciDevice<T> {
 			};
 
 			#[cfg(not(feature = "pci-ids"))]
-			let (class_name, vendor_name, device_name) = ("Unknown Class", "Unknown Vendor", "Unknown Device");
+			let (class_name, vendor_name, device_name) =
+				("Unknown Class", "Unknown Vendor", "Unknown Device");
 
 			// Output detailed readable information about this device.
 			write!(
diff --git a/src/fd/socket/tcp.rs b/src/fd/socket/tcp.rs
index 2649e94d15..44e5914523 100644
--- a/src/fd/socket/tcp.rs
+++ b/src/fd/socket/tcp.rs
@@ -172,8 +172,10 @@ impl ObjectInterface for Socket {
 			self.with(|socket| match socket.state() {
 				tcp::State::Closed | tcp::State::Closing | tcp::State::CloseWait => {
 					let available = PollEvent::POLLOUT
-						| PollEvent::POLLWRNORM | PollEvent::POLLWRBAND
-						| PollEvent::POLLIN | PollEvent::POLLRDNORM
+						| PollEvent::POLLWRNORM
+						| PollEvent::POLLWRBAND
+						| PollEvent::POLLIN
+						| PollEvent::POLLRDNORM
 						| PollEvent::POLLRDBAND;
 
 					let ret = event & available;