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Share more of the TYP_MASK handling and support rewriting TYP_MASK operands in rationalization (#103288)
* Share more of the TYP_MASK handling and support rewriting TYP_MASK operands in rationalization * Ensure we pass in TYP_MASK, not the simdType * Apply formatting patch * Fix copy/paste error, pass in clsHnd for the argument * Ensure that we normalize sigType before inserting the CvtMaskToVectorNode * Ensure that we get the vector node on Arm64 (ConvertVectorToMask has 2 ops)
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9 files changed

+292
-282
lines changed

9 files changed

+292
-282
lines changed

‎src/coreclr/jit/compiler.h‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3185,6 +3185,10 @@ class Compiler
31853185
GenTree* gtNewSimdAbsNode(
31863186
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize);
31873187

3188+
#if defined(TARGET_ARM64)
3189+
GenTree* gtNewSimdAllTrueMaskNode(CorInfoType simdBaseJitType, unsigned simdSize);
3190+
#endif
3191+
31883192
GenTree* gtNewSimdBinOpNode(genTreeOps op,
31893193
var_types type,
31903194
GenTree* op1,
@@ -3223,6 +3227,8 @@ class Compiler
32233227
CorInfoType simdBaseJitType,
32243228
unsigned simdSize);
32253229

3230+
GenTree* gtNewSimdCvtMaskToVectorNode(var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize);
3231+
32263232
GenTree* gtNewSimdCvtNode(var_types type,
32273233
GenTree* op1,
32283234
CorInfoType simdTargetBaseJitType,
@@ -3235,6 +3241,8 @@ class Compiler
32353241
CorInfoType simdSourceBaseJitType,
32363242
unsigned simdSize);
32373243

3244+
GenTree* gtNewSimdCvtVectorToMaskNode(var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize);
3245+
32383246
GenTree* gtNewSimdCreateBroadcastNode(
32393247
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize);
32403248

@@ -3516,12 +3524,6 @@ class Compiler
35163524

35173525
GenTreeIndir* gtNewMethodTableLookup(GenTree* obj);
35183526

3519-
#if defined(TARGET_ARM64)
3520-
GenTree* gtNewSimdConvertVectorToMaskNode(var_types type, GenTree* node, CorInfoType simdBaseJitType, unsigned simdSize);
3521-
GenTree* gtNewSimdConvertMaskToVectorNode(GenTreeHWIntrinsic* node, var_types type);
3522-
GenTree* gtNewSimdAllTrueMaskNode(CorInfoType simdBaseJitType, unsigned simdSize);
3523-
#endif
3524-
35253527
//------------------------------------------------------------------------
35263528
// Other GenTree functions
35273529

‎src/coreclr/jit/gentree.cpp‎

Lines changed: 77 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -21530,6 +21530,35 @@ GenTree* Compiler::gtNewSimdCeilNode(var_types type, GenTree* op1, CorInfoType s
2153021530
return gtNewSimdHWIntrinsicNode(type, op1, intrinsic, simdBaseJitType, simdSize);
2153121531
}
2153221532

21533+
//------------------------------------------------------------------------
21534+
// gtNewSimdCvtMaskToVectorNode: Convert a HW instrinsic mask node to a vector
21535+
//
21536+
// Arguments:
21537+
// type -- The type of the node to convert to
21538+
// op1 -- The node to convert
21539+
// simdBaseJitType -- the base jit type of the converted node
21540+
// simdSize -- the simd size of the converted node
21541+
//
21542+
// Return Value:
21543+
// The node converted to the given type
21544+
//
21545+
GenTree* Compiler::gtNewSimdCvtMaskToVectorNode(var_types type,
21546+
GenTree* op1,
21547+
CorInfoType simdBaseJitType,
21548+
unsigned simdSize)
21549+
{
21550+
assert(varTypeIsMask(op1));
21551+
assert(varTypeIsSIMD(type));
21552+
21553+
#if defined(TARGET_XARCH)
21554+
return gtNewSimdHWIntrinsicNode(type, op1, NI_EVEX_ConvertMaskToVector, simdBaseJitType, simdSize);
21555+
#elif defined(TARGET_ARM64)
21556+
return gtNewSimdHWIntrinsicNode(type, op1, NI_Sve_ConvertMaskToVector, simdBaseJitType, simdSize);
21557+
#else
21558+
#error Unsupported platform
21559+
#endif // !TARGET_XARCH && !TARGET_ARM64
21560+
}
21561+
2153321562
GenTree* Compiler::gtNewSimdCvtNode(var_types type,
2153421563
GenTree* op1,
2153521564
CorInfoType simdTargetBaseJitType,
@@ -21892,6 +21921,37 @@ GenTree* Compiler::gtNewSimdCvtNativeNode(var_types type,
2189221921
return gtNewSimdHWIntrinsicNode(type, op1, hwIntrinsicID, simdSourceBaseJitType, simdSize);
2189321922
}
2189421923

21924+
//------------------------------------------------------------------------
21925+
// gtNewSimdCvtVectorToMaskNode: Convert a HW instrinsic vector node to a mask
21926+
//
21927+
// Arguments:
21928+
// type -- The type of the mask to produce.
21929+
// op1 -- The node to convert
21930+
// simdBaseJitType -- the base jit type of the converted node
21931+
// simdSize -- the simd size of the converted node
21932+
//
21933+
// Return Value:
21934+
// The node converted to the a mask type
21935+
//
21936+
GenTree* Compiler::gtNewSimdCvtVectorToMaskNode(var_types type,
21937+
GenTree* op1,
21938+
CorInfoType simdBaseJitType,
21939+
unsigned simdSize)
21940+
{
21941+
assert(varTypeIsMask(type));
21942+
assert(varTypeIsSIMD(op1));
21943+
21944+
#if defined(TARGET_XARCH)
21945+
return gtNewSimdHWIntrinsicNode(TYP_MASK, op1, NI_EVEX_ConvertVectorToMask, simdBaseJitType, simdSize);
21946+
#elif defined(TARGET_ARM64)
21947+
// We use cmpne which requires an embedded mask.
21948+
GenTree* trueMask = gtNewSimdAllTrueMaskNode(simdBaseJitType, simdSize);
21949+
return gtNewSimdHWIntrinsicNode(TYP_MASK, trueMask, op1, NI_Sve_ConvertVectorToMask, simdBaseJitType, simdSize);
21950+
#else
21951+
#error Unsupported platform
21952+
#endif // !TARGET_XARCH && !TARGET_ARM64
21953+
}
21954+
2189521955
GenTree* Compiler::gtNewSimdCmpOpNode(
2189621956
genTreeOps op, var_types type, GenTree* op1, GenTree* op2, CorInfoType simdBaseJitType, unsigned simdSize)
2189721957
{
@@ -22569,19 +22629,15 @@ GenTree* Compiler::gtNewSimdCmpOpNode(
2256922629

2257022630
assert(intrinsic != NI_Illegal);
2257122631

22572-
#if defined(TARGET_XARCH)
2257322632
if (needsConvertMaskToVector)
2257422633
{
2257522634
GenTree* retNode = gtNewSimdHWIntrinsicNode(TYP_MASK, op1, op2, intrinsic, simdBaseJitType, simdSize);
22576-
return gtNewSimdHWIntrinsicNode(type, retNode, NI_EVEX_ConvertMaskToVector, simdBaseJitType, simdSize);
22635+
return gtNewSimdCvtMaskToVectorNode(type, retNode, simdBaseJitType, simdSize);
2257722636
}
2257822637
else
2257922638
{
2258022639
return gtNewSimdHWIntrinsicNode(type, op1, op2, intrinsic, simdBaseJitType, simdSize);
2258122640
}
22582-
#else
22583-
return gtNewSimdHWIntrinsicNode(type, op1, op2, intrinsic, simdBaseJitType, simdSize);
22584-
#endif
2258522641
}
2258622642

2258722643
GenTree* Compiler::gtNewSimdCmpOpAllNode(
@@ -27157,6 +27213,20 @@ bool GenTreeHWIntrinsic::OperIsCreateScalarUnsafe() const
2715727213
}
2715827214
}
2715927215

27216+
//------------------------------------------------------------------------
27217+
// OperIsBitwiseHWIntrinsic: Is the operation a bitwise logic operation.
27218+
//
27219+
// Arguments:
27220+
// oper -- The operation to check
27221+
//
27222+
// Return Value:
27223+
// Whether oper is a bitwise logic intrinsic node.
27224+
//
27225+
bool GenTreeHWIntrinsic::OperIsBitwiseHWIntrinsic(genTreeOps oper)
27226+
{
27227+
return (oper == GT_AND) || (oper == GT_AND_NOT) || (oper == GT_OR) || (oper == GT_XOR);
27228+
}
27229+
2716027230
//------------------------------------------------------------------------
2716127231
// OperIsBitwiseHWIntrinsic: Is this HWIntrinsic a bitwise logic intrinsic node.
2716227232
//
@@ -27165,8 +27235,8 @@ bool GenTreeHWIntrinsic::OperIsCreateScalarUnsafe() const
2716527235
//
2716627236
bool GenTreeHWIntrinsic::OperIsBitwiseHWIntrinsic() const
2716727237
{
27168-
genTreeOps Oper = HWOperGet();
27169-
return Oper == GT_AND || Oper == GT_OR || Oper == GT_XOR || Oper == GT_AND_NOT;
27238+
genTreeOps oper = HWOperGet();
27239+
return OperIsBitwiseHWIntrinsic(oper);
2717027240
}
2717127241

2717227242
//------------------------------------------------------------------------

‎src/coreclr/jit/gentree.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6505,6 +6505,8 @@ struct GenTreeHWIntrinsic : public GenTreeJitIntrinsic
65056505
}
65066506
#endif
65076507

6508+
static bool OperIsBitwiseHWIntrinsic(genTreeOps oper);
6509+
65086510
bool OperIsMemoryLoad(GenTree** pAddr = nullptr) const;
65096511
bool OperIsMemoryStore(GenTree** pAddr = nullptr) const;
65106512
bool OperIsMemoryLoadOrStore() const;

‎src/coreclr/jit/hwintrinsic.cpp‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1658,14 +1658,14 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
16581658
if (!varTypeIsMask(op2))
16591659
{
16601660
retNode->AsHWIntrinsic()->Op(2) =
1661-
gtNewSimdConvertVectorToMaskNode(retType, op2, simdBaseJitType, simdSize);
1661+
gtNewSimdCvtVectorToMaskNode(TYP_MASK, op2, simdBaseJitType, simdSize);
16621662
}
16631663
}
16641664

16651665
if (!varTypeIsMask(op1))
16661666
{
16671667
// Op1 input is a vector. HWInstrinsic requires a mask.
1668-
retNode->AsHWIntrinsic()->Op(1) = gtNewSimdConvertVectorToMaskNode(retType, op1, simdBaseJitType, simdSize);
1668+
retNode->AsHWIntrinsic()->Op(1) = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op1, simdBaseJitType, simdSize);
16691669
}
16701670

16711671
if (HWIntrinsicInfo::IsMultiReg(intrinsic))
@@ -1682,7 +1682,13 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
16821682
// HWInstrinsic returns a mask, but all returns must be vectors, so convert mask to vector.
16831683
assert(HWIntrinsicInfo::ReturnsPerElementMask(intrinsic));
16841684
assert(nodeRetType == TYP_MASK);
1685-
retNode = gtNewSimdConvertMaskToVectorNode(retNode->AsHWIntrinsic(), retType);
1685+
1686+
GenTreeHWIntrinsic* op = retNode->AsHWIntrinsic();
1687+
1688+
CorInfoType simdBaseJitType = op->GetSimdBaseJitType();
1689+
unsigned simdSize = op->GetSimdSize();
1690+
1691+
retNode = gtNewSimdCvtMaskToVectorNode(retType, op, simdBaseJitType, simdSize);
16861692
}
16871693
#endif // defined(TARGET_ARM64)
16881694

‎src/coreclr/jit/hwintrinsicarm64.cpp‎

Lines changed: 1 addition & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -2625,7 +2625,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
26252625
// HWInstrinsic requires a mask for op2
26262626
if (!varTypeIsMask(op2))
26272627
{
2628-
op2 = gtNewSimdConvertVectorToMaskNode(retType, op2, simdBaseJitType, simdSize);
2628+
op2 = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op2, simdBaseJitType, simdSize);
26292629
}
26302630

26312631
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseJitType, simdSize);
@@ -2646,48 +2646,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
26462646
return retNode;
26472647
}
26482648

2649-
//------------------------------------------------------------------------
2650-
// gtNewSimdConvertMaskToVectorNode: Convert a HW instrinsic vector node to a mask
2651-
//
2652-
// Arguments:
2653-
// node -- The node to convert
2654-
// simdBaseJitType -- the base jit type of the converted node
2655-
// simdSize -- the simd size of the converted node
2656-
//
2657-
// Return Value:
2658-
// The node converted to the a mask type
2659-
//
2660-
GenTree* Compiler::gtNewSimdConvertVectorToMaskNode(var_types type,
2661-
GenTree* node,
2662-
CorInfoType simdBaseJitType,
2663-
unsigned simdSize)
2664-
{
2665-
assert(varTypeIsSIMD(node));
2666-
2667-
// ConvertVectorToMask uses cmpne which requires an embedded mask.
2668-
GenTree* trueMask = gtNewSimdAllTrueMaskNode(simdBaseJitType, simdSize);
2669-
return gtNewSimdHWIntrinsicNode(TYP_MASK, trueMask, node, NI_Sve_ConvertVectorToMask, simdBaseJitType, simdSize);
2670-
}
2671-
2672-
//------------------------------------------------------------------------
2673-
// gtNewSimdConvertMaskToVectorNode: Convert a HW instrinsic mask node to a vector
2674-
//
2675-
// Arguments:
2676-
// node -- The node to convert
2677-
// type -- The type of the node to convert to
2678-
//
2679-
// Return Value:
2680-
// The node converted to the given type
2681-
//
2682-
GenTree* Compiler::gtNewSimdConvertMaskToVectorNode(GenTreeHWIntrinsic* node, var_types type)
2683-
{
2684-
assert(varTypeIsMask(node));
2685-
assert(varTypeIsSIMD(type));
2686-
2687-
return gtNewSimdHWIntrinsicNode(type, node, NI_Sve_ConvertMaskToVector, node->GetSimdBaseJitType(),
2688-
node->GetSimdSize());
2689-
}
2690-
26912649
//------------------------------------------------------------------------
26922650
// gtNewSimdEmbeddedMaskNode: Create an embedded mask
26932651
//

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