From d8eb2a596e8a4367752fb239d045fa93fcc4d487 Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Sun, 7 Sep 2025 22:53:56 +0800 Subject: [PATCH 1/3] armsom-sige5: enable edge build --- config/boards/armsom-sige5.csc | 2 +- .../rk3576-0001-sige5-wifi.patch | 120 +++++++++ .../rk3576-0002-sige5-usb.patch | 234 ++++++++++++++++++ .../rk3576-0003-rk3576-sdio.patch | 48 ++++ 4 files changed, 403 insertions(+), 1 deletion(-) create mode 100644 patch/kernel/archive/rockchip64-6.16/rk3576-0001-sige5-wifi.patch create mode 100644 patch/kernel/archive/rockchip64-6.16/rk3576-0002-sige5-usb.patch create mode 100644 patch/kernel/archive/rockchip64-6.16/rk3576-0003-rk3576-sdio.patch diff --git a/config/boards/armsom-sige5.csc b/config/boards/armsom-sige5.csc index 629028fa2b24..cee8001d1792 100644 --- a/config/boards/armsom-sige5.csc +++ b/config/boards/armsom-sige5.csc @@ -2,7 +2,7 @@ BOARD_NAME="ArmSoM Sige5" BOARDFAMILY="rk35xx" BOOTCONFIG="armsom-sige5-rk3576_defconfig" -KERNEL_TARGET="vendor" +KERNEL_TARGET="vendor|edge" FULL_DESKTOP="yes" BOOT_LOGO="desktop" BOOT_FDT_FILE="rockchip/rk3576-armsom-sige5.dtb" diff --git a/patch/kernel/archive/rockchip64-6.16/rk3576-0001-sige5-wifi.patch b/patch/kernel/archive/rockchip64-6.16/rk3576-0001-sige5-wifi.patch new file mode 100644 index 000000000000..98cee21acdc5 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.16/rk3576-0001-sige5-wifi.patch @@ -0,0 +1,120 @@ +From 358ccc1d8b242b8c659e5e177caef174624e8cb6 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Sat, 14 Jun 2025 22:14:35 +0400 +Subject: arm64: dts: rockchip: add version-independent WiFi/BT nodes on Sige5 + +ArmSoM Sige5 uses a soldered-on WiFi/BT module with WiFi on SDIO and BT +on UART. However, board v1.1 uses a Realtek based BL-M8852BS2, while +v1.2 uses a Broadcom based BW3752-50B1. They use the same pins and +controllers, but require different DT properties to enable. + +Thankfully, the WiFi part at least works without explicitly listing it in +the device tree, albeit without OOB interrupt functionality. + +Add required device tree nodes that do not depend on the board version so +that at least the WiFi module can appear on the SDIO bus. + +WiFi OOB interrupt and Bluetooth function support are not enabled here, as +they require module specific properties. + +Signed-off-by: Alexey Charkov +Link: https://lore.kernel.org/r/20250614-sige5-updates-v2-3-3bb31b02623c@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3576-armsom-sige5.dts | 57 ++++++++++++++++++++++ + 1 file changed, 57 insertions(+) + +(limited to 'arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts') + +diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +index 34e51cd71eac03..8f6d50febf830e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +@@ -205,6 +205,15 @@ vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v0_sys>; + }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&hym8563>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_reg_on>; ++ reset-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ }; + }; + + &combphy0_ps { +@@ -736,6 +745,30 @@ pcie_reset: pcie-reset { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; ++ ++ wireless-bluetooth { ++ bt_reg_on: bt-reg-on { ++ rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ host_wake_bt: host-wake-bt { ++ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ bt_wake_host: bt-wake-host { ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ wireless-wlan { ++ wifi_wake_host: wifi-wake-host { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ wifi_reg_on: wifi-reg-on { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; + }; + + &sai1 { +@@ -763,6 +796,23 @@ &sdhci { + status = "okay"; + }; + ++&sdio { ++ bus-width = <4>; ++ cap-sdio-irq; ++ disable-wp; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ no-sd; ++ no-mmc; ++ non-removable; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_s3>; ++ vqmmc-supply = <&vcc_1v8_s3>; ++ wakeup-source; ++ status = "okay"; ++}; ++ + &sdmmc { + bus-width = <4>; + cap-mmc-highspeed; +@@ -782,6 +832,13 @@ &uart0 { + status = "okay"; + }; + ++/* Used by Bluetooth modules, enabled in a version specific overlay */ ++&uart4 { ++ pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn &uart4m1_rtsn>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++}; ++ + &vop { + status = "okay"; + }; +-- +cgit 1.2.3-korg + diff --git a/patch/kernel/archive/rockchip64-6.16/rk3576-0002-sige5-usb.patch b/patch/kernel/archive/rockchip64-6.16/rk3576-0002-sige5-usb.patch new file mode 100644 index 000000000000..f8fb70147c28 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.16/rk3576-0002-sige5-usb.patch @@ -0,0 +1,234 @@ +From 64df8e2e207a2152201ef3515baacd8816c13282 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Thu, 19 Jun 2025 20:36:37 +0200 +Subject: arm64: dts: rockchip: enable USB on Sige5 + +The ArmSoM Sige5 has several USB ports: a Type-A USB 3 port (USB2 lines +going through a hub), a Type-A USB 2.0 port (also going through a hub), +a Type-C DC input port that has absolutely no USB data connection and a +Type-C port with USB3.2 Gen1x1 that's also the maskrom programming port. + +Enable these ports, and set the device role to be host for the host +ports. + +The data capable Type-C USB port uses a fusb302 for data role switching. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20250619-rk3576-sige5-usb-v5-2-9069a7e750e1@collabora.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3576-armsom-sige5.dts | 161 +++++++++++++++++++++ + 1 file changed, 161 insertions(+) + +(limited to 'arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts') + +diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +index 8f6d50febf830e..78add29f8a5c73 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +@@ -196,6 +196,30 @@ vcc_5v0_device: regulator-vcc-5v0-device { + vin-supply = <&vcc_12v0_dcin>; + }; + ++ vcc_5v0_typec0: regulator-vcc-5v0-typec0 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_otg0_pwren>; ++ regulator-name = "vcc_5v0_typec0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v0_device>; ++ }; ++ ++ vcc_5v0_usbhost: regulator-vcc-5v0-usbhost { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_host_pwren>; ++ regulator-name = "vcc_5v0_usbhost"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v0_device>; ++ }; ++ + vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_ufs_s0"; +@@ -216,6 +240,10 @@ sdio_pwrseq: sdio-pwrseq { + }; + }; + ++&combphy1_psu { ++ status = "okay"; ++}; ++ + &combphy0_ps { + status = "okay"; + }; +@@ -640,6 +668,58 @@ regulator-state-mem { + &i2c2 { + status = "okay"; + ++ usbc0: typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usbc0_interrupt>; ++ vbus-supply = <&vcc_5v0_typec0>; ++ ++ connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ data-role = "dual"; ++ /* fusb302 supports PD Rev 2.0 Ver 1.2 */ ++ pd-revision = /bits/ 8 <0x2 0x0 0x1 0x2>; ++ power-role = "source"; ++ source-pdos = ; ++ ++ altmodes { ++ displayport { ++ svid = /bits/ 16 <0xff01>; ++ vdo = <0xffffffff>; ++ }; ++ }; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usbc0_hs_ep: endpoint { ++ remote-endpoint = <&usb_drd0_hs_ep>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ usbc0_ss_ep: endpoint { ++ remote-endpoint = <&usb_drd0_ss_ep>; ++ }; ++ }; ++ port@2 { ++ reg = <2>; ++ usbc0_dp_ep: endpoint { ++ remote-endpoint = <&usbdp_phy_ep>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; +@@ -746,6 +826,24 @@ pcie_reset: pcie-reset { + }; + }; + ++ usb { ++ usb_host_pwren: usb-host-pwren { ++ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ usb_otg0_pwren: usb-otg0-pwren { ++ rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ usbc0_interrupt: usbc0-interrupt { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ usbc0_sbu1: usbc0-sbu1 { ++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ usbc0_sbu2: usbc0-sbu2 { ++ rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ + wireless-bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; +@@ -827,6 +925,23 @@ &sdmmc { + status = "okay"; + }; + ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ phy-supply = <&vcc_5v0_usbhost>; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +@@ -839,6 +954,52 @@ &uart4 { + uart-has-rtscts; + }; + ++&usb_drd0_dwc3 { ++ usb-role-switch; ++ dr_mode = "otg"; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usb_drd0_hs_ep: endpoint { ++ remote-endpoint = <&usbc0_hs_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ usb_drd0_ss_ep: endpoint { ++ remote-endpoint = <&usbc0_ss_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&usb_drd1_dwc3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usbdp_phy { ++ mode-switch; ++ orientation-switch; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usbc0_sbu1 &usbc0_sbu2>; ++ sbu1-dc-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; ++ sbu2-dc-gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ ++ port { ++ usbdp_phy_ep: endpoint { ++ remote-endpoint = <&usbc0_dp_ep>; ++ }; ++ }; ++}; ++ + &vop { + status = "okay"; + }; +-- +cgit 1.2.3-korg + diff --git a/patch/kernel/archive/rockchip64-6.16/rk3576-0003-rk3576-sdio.patch b/patch/kernel/archive/rockchip64-6.16/rk3576-0003-rk3576-sdio.patch new file mode 100644 index 000000000000..3073644d7954 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.16/rk3576-0003-rk3576-sdio.patch @@ -0,0 +1,48 @@ +From e490f854b46369b096f3d09c0c6a00f340425136 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Sat, 14 Jun 2025 22:14:34 +0400 +Subject: arm64: dts: rockchip: add SDIO controller on RK3576 + +RK3576 has one more SD/MMC controller than are currently listed in its +.dtsi, with the missing one intended as an SDIO controller. Add the +missing node (tested with the onboard WiFi module on ArmSoM Sige5 v1.2) + +Signed-off-by: Alexey Charkov +Link: https://lore.kernel.org/r/20250614-sige5-updates-v2-2-3bb31b02623c@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3576.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +(limited to 'arch/arm64/boot/dts/rockchip/rk3576.dtsi') + +diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi +index 1086482f047923..d3225d20baadd5 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi +@@ -1695,6 +1695,22 @@ sdmmc: mmc@2a310000 { + status = "disabled"; + }; + ++ sdio: mmc@2a320000 { ++ compatible = "rockchip,rk3576-dw-mshc"; ++ reg = <0x0 0x2a320000 0x0 0x4000>; ++ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>; ++ clock-names = "biu", "ciu"; ++ fifo-depth = <0x100>; ++ interrupts = ; ++ max-frequency = <200000000>; ++ pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>; ++ pinctrl-names = "default"; ++ power-domains = <&power RK3576_PD_SDGMAC>; ++ resets = <&cru SRST_H_SDIO>; ++ reset-names = "reset"; ++ status = "disabled"; ++ }; ++ + sdhci: mmc@2a330000 { + compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; + reg = <0x0 0x2a330000 0x0 0x10000>; +-- +cgit 1.2.3-korg + From a7089ce524baef398920d5920bf6e716f49bb340 Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Sun, 7 Sep 2025 22:54:29 +0800 Subject: [PATCH 2/3] rtl8852bs: enable build for rockchip64 --- lib/functions/compilation/patch/drivers_network.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/functions/compilation/patch/drivers_network.sh b/lib/functions/compilation/patch/drivers_network.sh index a387d88188f6..78760014d0af 100644 --- a/lib/functions/compilation/patch/drivers_network.sh +++ b/lib/functions/compilation/patch/drivers_network.sh @@ -363,10 +363,10 @@ driver_rtl8852bs() { # Wireless driver for Realtek 8852BS SDIO Wireless driver used in BananaPi F3 and Armsom Sige5 - if linux-version compare "${version}" ge 6.1 && [[ "${LINUXFAMILY}" == spacemit || "${LINUXFAMILY}" == rk35xx ]]; then + if linux-version compare "${version}" ge 6.1 && [[ "${LINUXFAMILY}" == spacemit || "${LINUXFAMILY}" == rk35xx || "${LINUXFAMILY}" == rockchip64 ]]; then # Attach to specific commit - local rtl8852bs_ver='commit:b7d94226641ef4687bc7f54ae6fa01b7e30f4b82' # Commit date: July 10, 2024 (please update when updating commit ref) + local rtl8852bs_ver='commit:8fa9401084686a645e0a6da359610cc8fce22dc5' # Commit date: July 10, 2024 (please update when updating commit ref) display_alert "Adding" "Wireless drivers for Realtek 8852BS SDIO chipset ${rtl8852bs_ver}" "info" @@ -408,7 +408,7 @@ driver_rtl8852bs() { # We have to enable specific platforms in the driver Makefile to enable specific driver tweaks, they are all "n" by default case ${LINUXFAMILY} in # For Rockchip devices, add family name here - rk35xx) + rk35xx|rockchip64) sed -i "s/CONFIG_PLATFORM_ARM_ROCKCHIP = n/CONFIG_PLATFORM_ARM_ROCKCHIP = y/g" "$kerneldir/drivers/net/wireless/realtek/rtl8852bs/Makefile" ;; # For Spacemit devices, add family name here From afe160b9ad7ab87b3083983f8ececf097b0cde4f Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Mon, 8 Sep 2025 00:16:48 +0800 Subject: [PATCH 3/3] rockchip64-6.16: enable RTL8852BS --- config/kernel/linux-rockchip64-edge.config | 1 + 1 file changed, 1 insertion(+) diff --git a/config/kernel/linux-rockchip64-edge.config b/config/kernel/linux-rockchip64-edge.config index 290c2f2aea28..8ddf2c5bfe5a 100644 --- a/config/kernel/linux-rockchip64-edge.config +++ b/config/kernel/linux-rockchip64-edge.config @@ -1110,6 +1110,7 @@ CONFIG_RTW89_8852BE=m CONFIG_RTW89_8852BTE=m CONFIG_RTW89_8852CE=m CONFIG_RTW89_8922AE=m +CONFIG_RTL8852BS=m CONFIG_RSI_91X=m # CONFIG_RSI_DEBUGFS is not set CONFIG_WFX=m